Multi-core Digital Signal Processor Research Articles

High-Precision Joint TDOA and FDOA Location System

Passive location based on TDOA (time difference of arrival) and FDOA (frequency difference of arrival) is the mainstream method for target localization. This paper proposes a fast time–frequency difference positioning method to address issues such as low accuracy, large computational resource utilization, and limited suitability for real-time signal processing in the conventional CAF (cross-ambiguity function)-based approach, aiming to complete the processing of the target radiation source to obtain the target parameters within a short timeframe. In the mixing product operation step of the CAF, a frequency-domain approach replaces the time-domain convolution operation in PW-ZFFT (pre-weighted Zoom-FFT) to reduce the computational load of the CAF. Additionally, a quadratic surface fitting method is used to enhance the accuracy of TDOA and FDOA. The localization solution is obtained using Newton’s method, which can provide more accurate results compared to analytical methods. Next, a signal processing platform is designed with FPGA (field-programmable gate array) and multi-core DSP (digital signal processor), and works by dividing and mapping the algorithm functional modules according to the hardware’s characteristics. We analyze the architectural advantages of multi-core DSP and design methods to improve program performance, such as EDMA transfer optimization, inline function optimization, and cache optimization. Finally, this paper constructs simulation tests in typical positioning scenarios and compares them to hardware measurement results, thus confirming the correctness and real-time capability of the program.

Efficient parallel implementation of Gaussian Mixture Model background subtraction algorithm on an embedded multi-core Digital Signal Processor

Scene segmentation is crucial in video processing applications, such as vehicle detection. The Gaussian Mixture Model (GMM) based background subtraction (BS) is a widely employed technique for scene segmentation. However, due to its high computational demands, an efficient parallel implementation is necessary. This paper proposes a parallelized implementation of the GMM algorithm on the C6678 digital signal processor (DSP), utilizing its eight cores. Three different parallelization approaches are presented: Open Multiprocessing (OpenMP), manually optimized method, and manually optimized method involving Direct Memory Access (DMA) engine. To evaluate their effectiveness, a metrics comparison is conducted using background truth images provided by the literature dataset references. The experimental results demonstrate that the proposed manually optimized method surpasses the current state-of-the-art. It achieves a remarkable parallel efficiency of approximately 99% for low and medium frame sizes and 83% and 79% for high-definition (HD) and full-HD resolution frames, respectively, when all eight cores are enabled. In contrast, the parallel efficiency obtained using OpenMP is only 45%.

Dynamic Yarn-Tension Detection Using Machine Vision Combined with a Tension Observer.

Machine vision can prevent additional stress on yarn caused by contact measurement, as well as the risk of hairiness and breakage. However, the speed of the machine vision system is limited by image processing, and the tension detection method based on the axially moving model does not take into account the disturbance on yarn caused by motor vibrations. Thus, an embedded system combining machine vision with a tension observer is proposed. The differential equation for the transverse dynamics of the string is established using Hamilton's principle and then solved. A field-programmable gate array (FPGA) is used for image data acquisition, and the image processing algorithm is implemented using a multi-core digital signal processor (DSP). To obtain the yarn vibration frequency in the axially moving model, the brightest centreline grey value of the yarn image is put forward as a reference to determine the feature line. The calculated yarn tension value is then combined with the value obtained using the tension observer based on an adaptive weighted data fusion method in a programmable logic controller (PLC). The results show that the accuracy of the combined tension is improved compared with the original two non-contact methods of tension detection at a faster update rate. The system alleviates the problem of inadequate sampling rate using only machine vision methods and can be applied to future real-time control systems.

Smart Multi-Agent Framework for Automated Audio Testing

With the widespread use of embedded software in consumer electronics, automotive industry, medical devices, and industrial environments, embedded software testing is gaining significance as an indispensable part of development and deployment of embedded products. With more than 20 years of research, development, and testing of various consumer technologies and products based on digital signal processors (DSPs) and advanced reduced instruction set computers (ARMs), we obtained insight into typical embedded development process and testing, and the pros and cons of various testing approaches and environments. In this paper, we propose the Smart Multi-Agent Framework based on IoT and Jenkins agents, customised for audio technologies in the Home Audio domain. We evaluated our solution on several complex immersive audio technologies implemented on a multicore DSP. Our uniform, customised, fully automated approach proved to be time efficient, error resilient, easy to replicate and use across all development, certification, and deployment phases of the product life cycle.

Research on key technologies of multi-core DSP in smart substation redundancy network testing

Aiming at the network characteristics of a smart substation redundant network with complex communication messages, a large amount of interactive data, and high real-time performance, the test model of multiple submachines in a High-Availability Seamless Redundancy (HSR) loop network is analyzed. The requirements of packet types, size, and transmission speed are evaluated, and a hardware solution based on a multi-core Digital Signal Processor (DSP) and Parallel architecture FPGA is designed. The multi-core interaction strategy of DSP software and the multi-port high-speed communication method of FPGA are proposed, and the inter-core communication (IPC) interrupts and shared memory to achieve fast data migration between cores, based on the Serial RapidIO (SRIO) to complete high-speed message transmission. The throughput, delay, packet loss rate, and error frame detection functions are realized, tested, and verified, providing theoretical and practical support for the evaluation of redundant network performance of smart substations.

Analysis of the Influence of Software and Hardware Noise on the Results of Digital Signal Processing

The achievement of a higher quality signal processing occurs, among other things, due to the complication of its processing algorithms, i. e., an increase in the amount of calculations. This processing must be carried out in real time. One of the ways to overcome this problem is to split a complex algorithm into several simpler parts that must be executed in parallel and then combined. For this purpose, digital computing platforms are used, which are built on the basis of various discrete elements, such as programmable logic integrated circuits, microcontrollers or multi-core digital signal processors. Based on the results of the research, a mathematical expression was obtained that shows that the final signal-to-noise ratio significantly depends on the processing frequency. This ratio also depends on the element base on the basis of which digital processing algorithms are implemented. Using the characteristics of individual chips as an example, it is shown that the use of certain chip types is preferable in some cases because it allows the processing to be implemented in a wider clock frequency range.

DSP TMS320C6678 Based SHVC Encoder Implementation and its Optimization

The programmable processors newest technologies, as for example the multicore Digital Signal Processors (DSP), offer a promising solution for overcoming the complexity of the real time video encoding application. In this paper, the SHVC video encoder was effectively implemented just on a single core among the eight cores of TMS320C6678 DSP for a Common Intermediate Format (CIF)input video sequence resolution(352x288). Performance optimization of the SHVC encoder had reached up 41% compared to its reference software enabling a real-time implementation of the SHVC encoder for CIF input videos sequence resolution. The proposed SHVC implementation was carried out on different quantization parameters (QP). Several experimental tests had proved our performance achievement for real-time encoding on TMS320C6678.

An efficient and scalable parallel mapping of pulse-Doppler radar signal processing chain on a multi-core DSP

Digital Pulse-Doppler radar chain consists of signal processing algorithms that require high computing power. Multi-processor and multi-core parallel embedded machines are one of the solutions to meet real-time constraints of many radar applications. In this paper, we proposed efficient and scalable parallelization methods of the Pulse-Doppler radar signal processing chain. First, we evaluated Open Multi Processing (OpenMP) to identify its best scheduling technique in order to exploit efficiently the available computing cores. Then, we have proposed new parallel and scalable approaches based on direct memory access (DMA) and inter-processor communication (IPC) techniques, combined with the best OpenMP scheduling method to accelerate radar signal processing chain. To prove the scalability of our proposed parallel approaches, two radar use cases with different real-time and memory constraints have been experienced. We used the eight cores C6678 digital signal processor (DSP) as a target for all our implementations. The obtained results show an overall parallel efficiency of 95%, which is better than the best state-of-the-art implementations.

Real-time Object Tracking Method based on Multi-Core DSP

In this paper, we propose a fast object tracking method used in real-time application. The tracking method is based on compact kernelized correlation filters. Traditional, gray values are used to describe target feature. In order to achieve relatively fast performance, we adopt Principal Component Analysis (PCA) to simplify Histogram of Gradient (HOG) as feature descriptor, which can significantly reduce computation resources. Our method is implemented on Texas Instruments (TI) multi-core digital signal processor (DSP) TMS320 C6657, which can achieve 60 frame per-second (fps). Finally, we conduct both quantitative and qualitative experiment to show the robustness and real-time performance of our method.

Parallel implementation of pulse compression method on a multi-core digital signal processor

Pulse compression algorithm is widely used in radar applications. It requires a huge processing power in order to be executed in real time. Therefore, its processing must be distributed along multiple processing units. The present paper proposes a real time platform based on the multi-core digital signal processor (DSP) C6678 from Texas Instruments (TI). The objective of this paper is the optimization of the parallel implementation of pulse compression algorithm over the eight cores of the C6678 DSP. Two parallelization approaches were implemented. The first approach is based on the open multi processing (OpenMP) programming interface, which is a software interface that helps to execute different sections of a program on a multi core processor. The second approach is an optimized method that we have proposed in order to distribute the processing and to synchronize the eight cores of the C6678 DSP. The proposed method gives the best performance. Indeed, a parallel efficiency of 94% was obtained when the eight cores were activated.

1.55-μm pulse coherent LIDAR with 10-km detection range

Recently, a 1.55-μm pulsed coherent Doppler LIDAR system using all fiber optical components was developed to achieve real-time measurements of wind fields. The system employs 100-μJ pulse energy at 10 kHz pulse repetition rate. In addition, the system consists of a fiber-based optical transceiver unit, a two-axis scanner, and a multicore digital signal processor (DSP) for real-time signal processing. With compact and mobile design, the LIDAR is easy to transport and deploy for different field campaigns. For a different application of LIDAR, the range resolution can change manually. A horizontal detection range of 10 km is achieved with the temporal and spatial resolution of 1 s and 30 m, respectively. Field experiments compared with an anemometer show that correlation coefficient of the different wind speed measurements is 0.953; the correlation coefficient for wind direction values is 0.967. Continuous wind profiles of the planetary boundary layer are presented to demonstrate the stability of the system.

Design and implementation of MIMO radar real‐time imaging system based on multicore DSP

Multiple-input multiple-output (MIMO) imaging radar is a new kind of new imaging radar in recent years. It can achieve faster data acquisition speed than the traditional ground-based SAR due to the ability to get a large number of multi-channel data in a short period of time. However, traditional single-core digital signal processors (DSPs) have limited space and ability to deal with such large amount of data. To solve this problem, a real-time image processing software architecture for MIMO imaging radar algorithm is designed and carried out based on TMS320C6678 DSP of Texas Instruments (TI), which is the highest-performance fixed/floating-point DSP based on TI's KeyStone multicore architecture. The efficient imaging algorithms mapping from Matlab to DSP is realised, with efficient task allocation, resource reuse of echo data, and processing variable, and using the method of multicore parallel processing.

Reconfigurable Instruction-Based Multicore Parallel Convolution and Its Application in Real-Time Template Matching

Convolution is widely used in scientific computational fields such as digital image processing and machine learning. However, these applications are difficult to execute in realtime because they are computationally intensive. This paper introduces a high-speed convolution solution that runs on our self-developed multicore digital signal processor (DSP). To optimize the convolution capability, we propose a convolution instruction and a convolution micro architecture in the design of a subcore. As a coprocessor, the designed subcore is integrated into a network-on-chip (NoC)-based multicore DSP. In the implementation of the multicore parallel convolution, an independent convolution task-partitioning and mapping scheme is proposed. Datablock storage and software prefetching mechanisms are used to hide the data transmission time during the calculation, improving the computing efficiency. We also develop a data reuse strategy that effectively reduces the data bandwidth requirements of multicore parallel convolution. The proposed methods are applied to correlation-based template matching, with the results showing that our convolution computing approach greatly improves the performance compared with the same operations run on a personal computer, a TMS320C6678 processor and an NVIDIA Quadro 1000M graphics processing unit (GPU).

An embedded system based on DSP platform and PCA-SVM algorithms for rapid beef meat freshness prediction and identification

Statistical and artificial intelligence learning algorithms such as Principal Component Analysis (PCA) and Support Vector Machine (SVM) are widely used in many meat quality assessment applications to classify and predict the freshness of beef meat. This paper presents the implementation of the PCA and SVM algorithms on an embedded system based on a Digital Signal Processor (DSP). A dataset of eighty-one hue, saturation, and intensity (HSI) beef meat images was used. The PCA is used as a projection and prediction model where the SVM is used for the classification and identification of the beef meat. Results obtained from PCA projection model on a desktop system using Matlab software show the projection of three groups which represent the degree of beef meat freshness during the days of cold storage. A perfect prediction of the new unknown samples was obtained by PCA prediction model. A successful rate 100% of classification and identification was obtained by SVM. The PCA and SVM methods were implemented on the C6678 multi-core DSP. The implementation results of these algorithms were similar as those obtained by Matlab software. The processing time of the algorithms measured on the embedded system was lower compared to the desktop system. The embedded platforms based on DSP as portable tools can be used to predict or identify the sample beef meat freshness anywhere and in real-time.

PHEFT: Pessimistic Image Processing Workflow Scheduling for DSP Clusters

We address image processing workflow scheduling problems on a multicore digital signal processor cluster. We present an experimental study of scheduling strategies that include task labeling, prioritization, resource selection, and digital signal processor scheduling. We apply these strategies in the context of executing the Ligo and Montage applications. To provide effective guidance in choosing a good strategy, we present a joint analysis of three conflicting goals based on performance degradation. A case study is given, and experimental results demonstrate that a pessimistic scheduling approach provides the best optimization criteria trade-offs. The Pessimistic Heterogeneous Earliest Finish Time scheduling algorithm performs well in different scenarios with a variety of workloads and cluster configurations.

High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation

Vision-based navigation has become increasingly important in a variety of space applications for enhancing autonomy and dependability. Future missions, such as active debris removal for remediating the low Earth orbit environment, will rely on novel high-performance avionics to support advanced image processing algorithms with substantial workloads. However, when designing new avionics architectures, constraints relating to the use of electronics in space present great challenges, further exacerbated by the need for significantly faster processing compared to conventional space-grade central processing units. With the long-term goal of designing high-performance embedded computers for space, in this paper, an extended study and tradeoff analysis of a diverse set of computing platforms and architectures (i.e., central processing units, multicore digital signal processors, graphics processing units, and field-programmable gate arrays) are performed with radiation-hardened and commercial off-the-shelf technology. Overall, the study involves more than 30 devices and 10 benchmarks, which are selected after exploring the algorithms and specifications required for vision-based navigation. The present analysis combines literature survey and in-house development/testing to derive a sizable consistent picture of all possible solutions. Among others, the results show that certain 28 nm system-on-chip devices perform faster than space-grade and embedded central processing units by 1–3 orders of magnitude, while consuming less than 10 W. Field-programmable gate array platforms provide the highest performance per watt ratio.

Optimizing Convolution Neural Network on the TI C6678 multicore DSP

Convolutional Neural Networks (CNNs) have become the most advanced algorithms for deep learning. They are widely used in image processing, object detection and automatic translation. As the demand for CNNs continues to increase, the platforms on which they are deployed continue to expand. As an excellent low-power, high-performance, embedded solution, Digital Signal Processor (DSP) is used frequently in many key areas. This paper attempts to deploy the CNN to Texas Instruments (TI)’s TMS320C6678 multi-core DSP and optimize the main operations (convolution) to accommodate the DSP structure. The efficiency of the improved convolution operation has increased by tens of times.

An Approach of Using General Purpose Graphics Processing Units in Modern Systems for Electronic Warfare

Modern systems for electronic warfare, especially systems for electronic support based on fast scanning wideband direction finders, are usually designed to achieve high scanning speed in order to provide high probability of detection of signals of interest. To achieve high scanning speed two parameters are important: the first is instantaneous bandwidth of a receiver and the second is processing speed. By increasing instantaneous bandwidth of the receiver, it is possible to increase scanning speed. However, increasing of instantaneous bandwidth has a direct impact at amount of processing power to keep the same or to increase processing speed. In modern systems for electronic support, scanning speed depends on instantaneous bandwidth of the receiver, frequency resolution, implemented methods for estimation of direction of arrival and required preprocessing and processing power of hardware. The latest computer system architectures being developed by the computer industry offers more processing power in a smaller footprint. Parallel computing has been rejuvenated with the development of multicore technologies such as Multicore Processors, Multicore Digital Signal Processors and General Purpose Graphics Processing Units. In this paper an approach of using GPGPUs in the wideband fast scanning direction finder has been considered. Some of the obtained results are also presented.

Real-Time Controller Based on FPGA and DSP for Solar Ground Layer Adaptive Optics Prototype System at 1-m NVST

Solar ground layer adaptive optics (GLAO), containing a large field of view (FOV) wavefront sensor (WFS) and one deformable mirror (DM), can be used to reduce and stabilize the seeing effectively over a wide FOV. As the brain of the GLAO system, the real-time controller (RTC) computes the commands to drive the DM according to the average wavefront errors measured by the multi-direction correlating Shack–Hartmann WFS, which is a time-consuming process. A customized RTC based on a high-speed field programming gate array and a multi-core digital signal processor was developed for the solar GLAO prototype system at the 1-m New Vacuum Solar Telescope. Several parallel acceleration techniques are used to reduce the computation time of the RTC. Compared with the previous RTCs, our RTC architecture has nearly no timing jitter. In this paper, the design of the RTC for our solar GLAO prototype will be introduced. The test results of the RTC are also presented. Moreover, the on-sky Sun observational results of the solar GLAO prototype are shown.

A comparison of stereo matching algorithms on multi-core Digital Signal Processor platform

Stereo Matching algorithms reconstruct a depth map from a pair of stereoscopic images. Stereo Matching algorithms are computationally intensive. Implementing efficient stereo matching algorithms on embedded systems is very challenging. This paper compares implementation efficiency and output quality of the state of the art dense stereo matching algorithms on the same multicore embedded system. The three different classes of stereo matching algorithms are local methods, semi-global methods and global methods. This paper compares three algorithms of the literature with a good trade-off between complexity and accuracy : Bilateral Filtering Aggregation (BFA, Local Method), One Dimension Belief Propagation (BP-1D, Semi Global Methods) and Semi Global Matching (SGM, Semi Global Methods). For the same input data the BFA, BP-1D and SGM were fully optimized and parallelized on the C6678 platform and run at respectively 10.7 ms, 4.1 ms and 47.1 ms.